In some techniques which the inventors of the present invention have studied, as for semiconductor devices, the following technique has been considered.
In recent years, along with improvement of operational frequency and increase of consumption current in LSIs (Large Scale Integrated Circuits) among semiconductor devices, power supply noise has been to be increasing. On the other hand, according to the trend of lowering operational voltage along with developments of semiconductor manufacturing process, noise margin has been decreased. This has made the power-supply noise design very difficult.
While means for reducing power noise differs by frequencies, for frequencies from several hundreds of kHz to several tens of MHz which are so-called the low frequency band to the medium frequency band, a noise countermeasure to reduce impedance by a decoupling capacitor on a printed wiring board has been made. Among the above said frequencies, the capacitance of the decoupling capacitor is a dominant parameter in lowering impedance for the lower frequencies (several hundreds of kHz to several MHz), and the value of the inductance connecting the decoupling capacitor and LSI is a dominant parameter for the higher frequencies (several MHz to several tens of MHz). In other words, it is indispensable to connect a decoupling capacitor having a large capacity to the power supply terminal of LSI with a low inductance for lowering impedance of the target frequency range. Further, it is required to adjust the kind, number and method of mounting decoupling capacitors so as to make the impedance equal to or smaller than a desired value compliant to the system.
In FIG. 9, an example of mounting a decoupling capacitor is shown. FIG. 9 is a planer view showing an example of a configuration of a memory module which has been studied as a premise of the present invention. As shown in FIG. 9, a plurality of LSIs 902 such as DRAMs are mounted on a printed wiring board 901, and a decoupling capacitor 903 is arranged at the vicinity of a power terminal of each LSI 902 to be connected the power terminal, so that lower impedance and lower inductance can be obtained.
Note that, the inventors of the present invention have had a prior art search based on the result of their invention. As a result, they extracted Japanese Patent Application Laid-Open Publication No. 2006-216755 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2005-294383 (Patent Document 2).
Patent Document 1 has, as a whole, a main subject about embedding a capacitor in a sheet shape on an interposer board, where a thin-film capacitor is buried in the interposer, thereby achieving a low-ESL (Equivalent Series inductance) structure configured in combination with through-electrodes. But it does not use a thin-film capacitor to connect with a chip part on the printed wiring board unlike the present invention.
In addition, Patent Document 2 has, as a whole, a main subject about embedding a decoupling capacitor on a capacitor-mounting wiring board, where a capacitor is mounted on the capacitor-mounting wiring board so that, when a current is fed to the capacitor, the direction of the current becomes opposite to a current flowing through a wiring layer, thereby achieving low ESL. While Patent Document 2 describes a thin-film capacitor, the thin-film capacitor is not used as a power-supply path.